#ifndef __SWM120_H__
#define __SWM120_H__


/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */

typedef enum IRQn
{
/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
  NonMaskableInt_IRQn    	= -14,    /*!< 2 Non Maskable Interrupt                             */
  HardFault_IRQn	       	= -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                     */
  SVCall_IRQn              	= -5,     /*!< 11 Cortex-M0 SV Call Interrupt                       */
  PendSV_IRQn              	= -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                       */
  SysTick_IRQn             	= -1,     /*!< 15 Cortex-M0 System Tick Interrupt                   */

/******  DEMO Cortex-M0 specific Interrupt Numbers ********************************************/
  GPIO0_IRQn                = 0,      /*!< GPIO Interrupt                                       */                                       /*!< maximum of 32 Interrupts are possible                */
  GPIO1_IRQn         		= 1,
  BOD_IRQn					= 2,
  WDT_IRQn        			= 3,
  TIMER0_IRQn				= 4,
  PWM_IRQn        			= 5,
  ADC_IRQn         			= 6,
  IRQ7_IRQn         		= 7,
  UART_IRQn         	  	= 8,
  SSI_IRQn         		    = 9,
  IRQ10_IRQn         		= 10,
  TIMER1_IRQn    			= 11,
  GPIO2_IRQn         		= 12,
  GPIO3_IRQn         		= 13,
  GPIO4_IRQn         		= 14,
  GPIO5_IRQn        	 	= 15,
  GPIO6_IRQn         		= 16,
  GPIO7_IRQn       			= 17,
  TIMER2_IRQn  				= 18,
  TIMER3_IRQn				= 19,
  IRQ20_IRQn         		= 20,
  IRQ21_IRQn         		= 21,  
  GPIO8_IRQn       			= 22,
  GPIO9_IRQn      		 	= 23,
  GPIO10_IRQn       		= 24,
  GPIO11_IRQn       		= 25,
  IRQ26_IRQn         		= 26,
  IRQ27_IRQn         		= 27,
  IRQ28_IRQn         		= 28,
  IRQ29_IRQn         		= 29,
  PID_IRQn         			= 30, 
  IRQ31_IRQn         		= 31
} IRQn_Type;


/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT           0       /*!< UART does not provide a MPU present or not       */
#define __NVIC_PRIO_BITS        2       /*!< UART Supports 2 Bits for the Priority Levels     */
#define __Vendor_SysTickConfig  0       /*!< Set to 1 if different SysTick Config is used         */

#if   defined ( __CC_ARM )
  #pragma anon_unions
#endif

#include <stdio.h>
#include "core_cm0.h"                   /* Cortex-M0 processor and core peripherals               */
#include "system_SWM120.h"          	



/**
 * Initialize the system clock
 *
 * @param  none
 * @return none
 *
 * @brief  Setup the microcontroller system
 *         Initialize the PLL and update the SystemFrequency variable
 */
extern void SystemInit (void);


/******************************************************************************/
/*                Device Specific Peripheral registers structures             */
/******************************************************************************/

typedef struct{
	union {
		__IO  uint32_t u32OPA_CMP; 
		struct {
			__IO  uint32_t CMP_REFP	: 4;	//比较器正端内部基准电压 = 0.30+0.15*[0..3]
			__IO  uint32_t OP0_MODE : 4;	//000 保留								001 关闭比较器/放大器模块
											//010   迟滞比较器，ADC接受片外信号		011   迟滞比较器，ADC不接受片外信号
											//100 非迟滞比较器，ADC接受片外信号		101 非迟滞比较器，ADC不接受片外信号
											//110 放大器模式，  ADC接受片外信号		111 放大器模式，  ADC不接受片外信号
			__IO  uint32_t OP1_MODE : 4;
			__IO  uint32_t OP2_MODE : 4;
			__IO  uint32_t RESERVED :16;
		} OPA_CMP;
	};	
		
	__IO  uint32_t SPI_CTL;   
            
	__IO  uint32_t RESERVE[30];
    
    union {
        __IO  uint32_t u32PORTA_SEL; 
        struct {
            __IO  uint32_t PA00: 2;     //00 GPIO       01 SSI_CK       10/11 ADC0
            __IO  uint32_t PA01: 2;     //00 GPIO       01 SSI_RX       10/11 ADC1
            __IO  uint32_t PA02: 2;     //00 GPIO       01 SSI_TX       10/11 ADC2
            __IO  uint32_t PA03: 2;     //00 GPIO       01 PWM1         10/11 ADC3
            __IO  uint32_t PA04: 2;     //00 GPIO       01 PWM2         10/11 ADC4
            __IO  uint32_t PA05: 2;     //00 GPIO       01 PWM3         10/11 ADC5/OP0O
            __IO  uint32_t PA06: 2;     //00 GPIO       01 UART_RX      10/11 OP0N
            __IO  uint32_t PA07: 2;     //00 GPIO       01 UART_TX      10/11 OP0P
            __IO  uint32_t PA08: 2;     //00 GPIO       01 PWM4         10/11 --
            __IO  uint32_t PA09: 2;     //00 GPIO       01 TMR2         10/11 OP1N
            __IO  uint32_t PA10: 2;     //00 GPIO       01 SSI_SS       10/11 OP2N
            __IO  uint32_t PA11: 2;     //00 GPIO       01 PWM5         10/11 --
            __I  uint32_t RESERVE:8; 
        } PORTA_SEL;
    };
	           
    union {
        __IO  uint32_t u32PORTB_SEL; 
        struct {
            __IO  uint32_t PB00: 2;     //00 GPIO       01 TMR0         10/11 CLK+
            __IO  uint32_t PB01: 2;     //00 GPIO       01 TMR1         10/11 CLK-
            __IO  uint32_t PB02: 2;     //00 GPIO       01 SWCLK        10/11 --
            __IO  uint32_t PB03: 2;     //00 GPIO       01 SWDIO        10/11 --
            __IO  uint32_t PB04: 2;     //00 GPIO       01 PWM0         10/11 --
            __I  uint32_t RESERVE:22; 
        } PORTB_SEL;
    };
	
    union {
        __IO  uint32_t u32PORTC_SEL; 
        struct {
            __IO  uint32_t PC00: 2;     //00 GPIO       01 TMR1         10/11 ADC6/OP1O
            __IO  uint32_t PC01: 2;     //00 GPIO       01 TMR3         10/11 OP1P
            __IO  uint32_t PC02: 2;     //00 GPIO       01 SSI_SS       10/11 OP2P
            __IO  uint32_t PC03: 2;     //00 GPIO       01 SSI_CK       10/11 ADC7/OP2O
            __IO  uint32_t PC04: 2;     //00 GPIO       01 SSI_RX       10/11 --
            __IO  uint32_t PC05: 2;     //00 GPIO       01 SSI_TX       10/11 --
            __IO  uint32_t PC06: 2;     //00 GPIO       01 UART_RX      10/11 --
            __IO  uint32_t PC07: 2;     //00 GPIO       01 UART_TX      10/11 --
            __I  uint32_t RESERVE:16; 
        } PORTC_SEL;
    };
    
	__IO  uint32_t RESERVE1;

    union {								//上拉下拉模式切换后必须延时才能够起作用，延时时长须大于96uS
        __IO  uint32_t u32PORTA_PULLU; 
        struct {
            __IO  uint32_t PA00: 1;     //0 上拉关闭        1 上拉开启
            __IO  uint32_t PA01: 1;
            __IO  uint32_t PA02: 1;
            __IO  uint32_t PA03: 1;
            __IO  uint32_t PA04: 1;
            __IO  uint32_t PA05: 1;
            __IO  uint32_t PA06: 1;
            __IO  uint32_t PA07: 1;
            __IO  uint32_t PA08: 1;
            __IO  uint32_t PA09: 1;
            __IO  uint32_t PA10: 1;
            __IO  uint32_t PA11: 1;
            __I  uint32_t RESERVE:20;
        } PORTA_PULLU;  
    };
    
    union {
        __IO  uint32_t u32PORTB_PULLU; 
        struct {
            __IO  uint32_t PB00: 1;     //0 上拉关闭        1 上拉开启
            __IO  uint32_t PB01: 1;
            __IO  uint32_t PB02: 1;
            __IO  uint32_t PB03: 1;
            __IO  uint32_t PB04: 1;
            __I  uint32_t RESERVE:27;
        } PORTB_PULLU;  
    };
    
    union {
       __IO  uint32_t u32PORTC_PULLU; 
       struct {
           __IO  uint32_t PC00: 1;     //0 上拉关闭        1 上拉开启
           __IO  uint32_t PC01: 1;
           __IO  uint32_t PC02: 1;
           __IO  uint32_t PC03: 1;
           __IO  uint32_t PC04: 1;
           __IO  uint32_t PC05: 1;
           __IO  uint32_t PC06: 1;
           __IO  uint32_t PC07: 1;
           __I  uint32_t RESERVE:24;
       } PORTC_PULLU;  
    };

	__IO  uint32_t RESERVE2;

    union {
       __IO  uint32_t u32PORTA_PULLD; 
       struct {
           __IO  uint32_t PA00: 1;     //0 下拉关闭        1 下拉开启
           __IO  uint32_t PA01: 1;
           __IO  uint32_t PA02: 1;
           __IO  uint32_t PA03: 1;
           __IO  uint32_t PA04: 1;
           __IO  uint32_t PA05: 1;
           __IO  uint32_t PA06: 1;
           __IO  uint32_t PA07: 1;
           __IO  uint32_t PA08: 1;
           __IO  uint32_t PA09: 1;
           __IO  uint32_t PA10: 1;
           __IO  uint32_t PA11: 1;
           __I  uint32_t RESERVE:20;
       } PORTA_PULLD;  
    };
    
    union {
        __IO  uint32_t u32PORTB_PULLD; 
        struct {
            __IO  uint32_t PB00: 1;     //0 下拉关闭        1 下拉开启
            __IO  uint32_t PB01: 1;
            __IO  uint32_t PB02: 1;
            __IO  uint32_t PB03: 1;
            __IO  uint32_t PB04: 1;
            __I  uint32_t RESERVE:27;
        } PORTB_PULLD;  
    };
           
    union {
        __IO  uint32_t u32PORTC_PULLD; 
        struct {
            __IO  uint32_t PC00: 1;     //0 下拉关闭        1 下拉开启
            __IO  uint32_t PC01: 1;
            __IO  uint32_t PC02: 1;
            __IO  uint32_t PC03: 1;
            __IO  uint32_t PC04: 1;
            __IO  uint32_t PC05: 1;
            __IO  uint32_t PC06: 1;
            __IO  uint32_t PC07: 1;
            __I  uint32_t RESERVE:24;
        } PORTC_PULLD;  
    };
  
	__IO  uint32_t RESERVE3;
	           
    union {
        __IO  uint32_t u32PORTA_OPEND; 
        struct {
            __IO  uint32_t PA00: 1;     //0 推挽模式        1 开漏模式
            __IO  uint32_t PA01: 1;
            __IO  uint32_t PA02: 1;
            __IO  uint32_t PA03: 1;
            __IO  uint32_t PA04: 1;
            __IO  uint32_t PA05: 1;
            __IO  uint32_t PA06: 1;
            __IO  uint32_t PA07: 1;
            __IO  uint32_t PA08: 1;
            __IO  uint32_t PA09: 1;
            __IO  uint32_t PA10: 1;
            __IO  uint32_t PA11: 1;
            __I  uint32_t RESERVE:20;
        } PORTA_OPEND;  
    };
    
    union {
        __IO  uint32_t u32PORTB_OPEND; 
        struct {
            __IO  uint32_t PB00: 1;     //0 推挽模式        1 开漏模式
            __IO  uint32_t PB01: 1;
            __IO  uint32_t PB02: 1;
            __IO  uint32_t PB03: 1;
            __IO  uint32_t PB04: 1;
            __I  uint32_t RESERVE:27;
        } PORTB_OPEND;  
    };
            
    union {
        __IO  uint32_t u32PORTC_OPEND; 
        struct {
           __IO  uint32_t PC00: 1;     //0 推挽模式        1 开漏模式
           __IO  uint32_t PC01: 1;
           __IO  uint32_t PC02: 1;
           __IO  uint32_t PC03: 1;
           __IO  uint32_t PC04: 1;
           __IO  uint32_t PC05: 1;
           __IO  uint32_t PC06: 1;
           __IO  uint32_t PC07: 1;
           __I  uint32_t RESERVE:24;
        } PORTC_OPEND;  
    };
} PORT_T;

typedef struct 
{
	union {
		__IO uint32_t u32DAT;
		struct {
			__IO uint32_t DAT_0: 1;
			__IO uint32_t DAT_1: 1;
			__IO uint32_t DAT_2: 1;
			__IO uint32_t DAT_3: 1;
			__IO uint32_t DAT_4: 1;
			__IO uint32_t DAT_5: 1;
			__IO uint32_t DAT_6: 1;
			__IO uint32_t DAT_7: 1;
			__IO uint32_t DAT_8: 1;
			__IO uint32_t DAT_9: 1;
			__IO uint32_t DAT_10:1;
			__IO uint32_t DAT_11:1;
			__IO uint32_t DAT_12:1;
			__IO uint32_t DAT_13:1;
			__IO uint32_t DAT_14:1;
			__IO uint32_t DAT_15:1;
			__I  uint32_t RESERVE:16; 
		} DAT;
	};

	union {
		__IO uint32_t u32DIR;
		struct {
			__IO uint32_t DIR_0: 1;
			__IO uint32_t DIR_1: 1;
			__IO uint32_t DIR_2: 1;
			__IO uint32_t DIR_3: 1;
			__IO uint32_t DIR_4: 1;
			__IO uint32_t DIR_5: 1;
			__IO uint32_t DIR_6: 1;
			__IO uint32_t DIR_7: 1;
			__IO uint32_t DIR_8: 1;
			__IO uint32_t DIR_9: 1;
			__IO uint32_t DIR_10:1;
			__IO uint32_t DIR_11:1;
			__IO uint32_t DIR_12:1;
			__IO uint32_t DIR_13:1;
			__IO uint32_t DIR_14:1;
			__IO uint32_t DIR_15:1;
			__I  uint32_t RESERVE:16; 
		} DIR;
	};
} GPIO_T;

typedef struct
{
	union {
		__IO uint32_t u32EXT;
		struct {
			__IO uint32_t EXT0: 1;
			__IO uint32_t EXT1: 1;
			__IO uint32_t EXT2: 1;
			__IO uint32_t EXT3: 1;
			__IO uint32_t EXT4: 1;
			__IO uint32_t EXT5: 1;
			__IO uint32_t EXT6: 1;
			__IO uint32_t EXT7: 1;
			__IO uint32_t EXT8: 1;
			__IO uint32_t EXT9: 1;
			__IO uint32_t EXT10:1;
			__IO uint32_t EXT11:1;
			__IO uint32_t EXT12:1;
			__IO uint32_t EXT13:1;
			__IO uint32_t EXT14:1;
			__IO uint32_t EXT15:1;
			__I  uint32_t RESERVE:16; 
		} EXT;
	};
} GPIO_EXT_T;

typedef struct 
{
	union {
		__IO uint32_t u32INTEN;
		struct {
			__IO uint32_t INTEN0: 1;
			__IO uint32_t INTEN1: 1;
			__IO uint32_t INTEN2: 1;
			__IO uint32_t INTEN3: 1;
			__IO uint32_t INTEN4: 1;
			__IO uint32_t INTEN5: 1;
			__IO uint32_t INTEN6: 1;
			__IO uint32_t INTEN7: 1;
			__IO uint32_t INTEN8: 1;
			__IO uint32_t INTEN9: 1;
			__IO uint32_t INTEN10:1;
			__IO uint32_t INTEN11:1;
			__IO uint32_t INTEN12:1;
			__IO uint32_t INTEN13:1;
			__IO uint32_t INTEN14:1;
			__IO uint32_t INTEN15:1;
			__I  uint32_t RESERVE:16; 
		} INTEN;
	};

	union {
		__IO uint32_t u32INTMSK;
		struct {
			__IO uint32_t INTMSK0: 1;
			__IO uint32_t INTMSK1: 1;
			__IO uint32_t INTMSK2: 1;
			__IO uint32_t INTMSK3: 1;
			__IO uint32_t INTMSK4: 1;
			__IO uint32_t INTMSK5: 1;
			__IO uint32_t INTMSK6: 1;
			__IO uint32_t INTMSK7: 1;
			__IO uint32_t INTMSK8: 1;
			__IO uint32_t INTMSK9: 1;
			__IO uint32_t INTMSK10:1;
			__IO uint32_t INTMSK11:1;
			__IO uint32_t INTMSK12:1;
			__IO uint32_t INTMSK13:1;
			__IO uint32_t INTMSK14:1;
			__IO uint32_t INTMSK15:1;
			__I  uint32_t RESERVE:16; 
		} INTMSK;
	};

	union {
		__IO uint32_t u32INTMODE;			//0 电平触发	1 边沿触发
		struct {
			__IO uint32_t INTMODE0: 1;
			__IO uint32_t INTMODE1: 1;
			__IO uint32_t INTMODE2: 1;
			__IO uint32_t INTMODE3: 1;
			__IO uint32_t INTMODE4: 1;
			__IO uint32_t INTMODE5: 1;
			__IO uint32_t INTMODE6: 1;
			__IO uint32_t INTMODE7: 1;
			__IO uint32_t INTMODE8: 1;
			__IO uint32_t INTMODE9: 1;
			__IO uint32_t INTMODE10:1;
			__IO uint32_t INTMODE11:1;
			__IO uint32_t INTMODE12:1;
			__IO uint32_t INTMODE13:1;
			__IO uint32_t INTMODE14:1;
			__IO uint32_t INTMODE15:1;
			__I  uint32_t RESERVE:16; 
		} INTMODE;
	};
	
	union {
		__IO uint32_t u32INTLEVEL;			//0 低电平/下降沿触发		1 高电平/上升沿触发
		struct {
			__IO uint32_t INTLEVEL0: 1;
			__IO uint32_t INTLEVEL1: 1;
			__IO uint32_t INTLEVEL2: 1;
			__IO uint32_t INTLEVEL3: 1;
			__IO uint32_t INTLEVEL4: 1;
			__IO uint32_t INTLEVEL5: 1;
			__IO uint32_t INTLEVEL6: 1;
			__IO uint32_t INTLEVEL7: 1;
			__IO uint32_t INTLEVEL8: 1;
			__IO uint32_t INTLEVEL9: 1;
			__IO uint32_t INTLEVEL10:1;
			__IO uint32_t INTLEVEL11:1;
			__IO uint32_t INTLEVEL12:1;
			__IO uint32_t INTLEVEL13:1;
			__IO uint32_t INTLEVEL14:1;
			__IO uint32_t INTLEVEL15:1;
			__I  uint32_t RESERVE:16; 
		} INTLEVEL;
	};
	
	union {
		__IO uint32_t u32INTSTAT;
		struct {
			__IO uint32_t INTSTAT0: 1;
			__IO uint32_t INTSTAT1: 1;
			__IO uint32_t INTSTAT2: 1;
			__IO uint32_t INTSTAT3: 1;
			__IO uint32_t INTSTAT4: 1;
			__IO uint32_t INTSTAT5: 1;
			__IO uint32_t INTSTAT6: 1;
			__IO uint32_t INTSTAT7: 1;
			__IO uint32_t INTSTAT8: 1;
			__IO uint32_t INTSTAT9: 1;
			__IO uint32_t INTSTAT10:1;
			__IO uint32_t INTSTAT11:1;
			__IO uint32_t INTSTAT12:1;
			__IO uint32_t INTSTAT13:1;
			__IO uint32_t INTSTAT14:1;
			__IO uint32_t INTSTAT15:1;
			__I  uint32_t RESERVE:16; 
		} INTSTAT;
	};

	union {
		__IO uint32_t u32INTRAWS;
		struct {
			__IO uint32_t INTRAWS0: 1;
			__IO uint32_t INTRAWS1: 1;
			__IO uint32_t INTRAWS2: 1;
			__IO uint32_t INTRAWS3: 1;
			__IO uint32_t INTRAWS4: 1;
			__IO uint32_t INTRAWS5: 1;
			__IO uint32_t INTRAWS6: 1;
			__IO uint32_t INTRAWS7: 1;
			__IO uint32_t INTRAWS8: 1;
			__IO uint32_t INTRAWS9: 1;
			__IO uint32_t INTRAWS10:1;
			__IO uint32_t INTRAWS11:1;
			__IO uint32_t INTRAWS12:1;
			__IO uint32_t INTRAWS13:1;
			__IO uint32_t INTRAWS14:1;
			__IO uint32_t INTRAWS15:1;
			__I  uint32_t RESERVE:16; 
		} INTRAWS;
	};

	__I  uint32_t RESERVE3;

	union {
		__IO uint32_t u32INTCLR;
		struct {
			__IO uint32_t INTCLR0: 1;
			__IO uint32_t INTCLR1: 1;
			__IO uint32_t INTCLR2: 1;
			__IO uint32_t INTCLR3: 1;
			__IO uint32_t INTCLR4: 1;
			__IO uint32_t INTCLR5: 1;
			__IO uint32_t INTCLR6: 1;
			__IO uint32_t INTCLR7: 1;
			__IO uint32_t INTCLR8: 1;
			__IO uint32_t INTCLR9: 1;
			__IO uint32_t INTCLR10:1;
			__IO uint32_t INTCLR11:1;
			__IO uint32_t INTCLR12:1;
			__IO uint32_t INTCLR13:1;
			__IO uint32_t INTCLR14:1;
			__IO uint32_t INTCLR15:1;
			__I  uint32_t RESERVE:16; 
		} INTCLR;
	};
} EXTI_T;


typedef struct
{
	union {
		__I	 uint32_t RBR;
		__O	 uint32_t THR;
		__IO uint32_t DLL;
	};

	union {
		__IO uint32_t DLH;

		union {
			__IO uint32_t u32IER;
			struct {
				__IO uint32_t RBR_IEN : 1;	//RBR data available 和  charater timeout
				__IO uint32_t THR_IEN : 1;
				__IO uint32_t LSR_IEN : 1;
				__I  uint32_t RESERVE0: 4;
				__IO uint32_t LVL_IEN : 1;	//该为置1时，THRE中断将不再由LSR寄存器中的THRE标志触发，而是由FCR[4..5]控制
											//并且THRE标志位的意义也不再指示THR空，而是指示TX FIFO满
				__I  uint32_t RESERVE1:24;
			}IER;
		};	
	};

	union{
		union {
			__I  uint32_t u32IIR;
			struct {
				__I  uint32_t INT_ID  : 4;	//0001 无中断		0010 THR empty		0100 RBR data available		
											//0110 reciver line status		1100 charater timeout
				__I  uint32_t RESERVE0: 2;
				__I  uint32_t FIFO_EN : 2;	//指示当前是否FIFO被使能
				__I  uint32_t RESERVE1:24;
			} IIR;
		};

		__O  uint32_t FCR;	//[0] FIFO使能（只写）		[1] RXFIFO复位（只写）		[2] TXFIFO复位（只写）
							//[4..5] TXFIFO空触发	00 FIFO空		01 2字节		10 4字节		11 8字节
							//[6..7] RXFIFO满触发	00 有1字节		01 4字节		10 8字节		11 14字节		 
	};						//注：在RXFIFO使能时，LSR.DR为1表示RXFIFO中至少有一个字节数据；而IER.RBR_IEN中断在RXFIFO中字节达到触发水平时产生中断

	union {
		__IO uint32_t u32LCR;
		struct {
			__IO uint32_t DLEN : 2;			//00 5位		01 6位		10 7位		11 8位
			__IO uint32_t STOP : 1;			//0 1位		1 2位
			__IO uint32_t PEN  : 1;
			__IO uint32_t EPS  : 1;
			__IO uint32_t RESERVE0: 1;
			__IO uint32_t BC   : 1;			//Break Control，used to cause a break condition to be transmitted to the receiving device
			__IO uint32_t DLAB : 1;
			__I  uint32_t RESERVE1:24;	
		} LCR;
	};	
	
	__I  uint32_t RESERVE0;
		
	union {							
		__I  uint32_t u32LSR;
		struct {
			__I  uint32_t DR : 1;			//Data Ready 指示RBR或RX FIFO中至少包含一个字符
			__I  uint32_t OE : 1;			//在非FIFO模式下，新数据会覆盖掉旧的数据
											//在  FIFO模式下，新来的数据会被直接丢掉
			__I  uint32_t PE : 1;
			__I  uint32_t FE : 1;
			__I  uint32_t BI : 1;
			__I  uint32_t THRE : 1;			//THR空（FIFO模式下表示FIFO空）
			__I  uint32_t TEMT : 1;			//THR与TSR同时为空时置位
			__I  uint32_t RFE : 1;			//RX FIFO Error，只在使能FIFO时有意义，表示在RXFIFO中至少有一个校验错误、帧错误、break indication
			__I  uint32_t RESERVE1:24;	
		} LSR;
	};
	
	__I  uint32_t RESERVE1[25];
	
	union {	
		__I  uint32_t u32MSR;
		struct {
			__I  uint32_t BUSY : 1;
			__I  uint32_t RESERVE1:31;
		} USR;
	};
} UART_T;

typedef struct{
	union {
		__IO uint32_t u32CR0;
		struct {
			__IO uint32_t DFS : 4;				//Data Frame Lenght Select，[3..0]+1位，且[3..0] > 2 
			__IO uint32_t FRF : 2;				//Frame Format 00: SPI		01 SSP		10 Microwire
			__IO uint32_t CPHA : 1;
			__IO uint32_t CPOL : 1;
			__IO uint32_t TMOD : 2;				//Transmit Mode 00 发送和接收		01 仅发送		10 仅接收		11 EEPROM读
			__IO uint32_t RESERVE0: 1;
			__IO uint32_t SRL : 1;				//Shift Register Loop
			__IO uint32_t CFS : 4;				//Control Frame Size（Microwire）
			__IO uint32_t RESERVE1:16;
		} CR0;
	};
	
	union { 							
		__IO uint32_t u32CR1;
		struct {
			__IO uint32_t NDF : 16;				//Number of Data Frames（Microwire）
			__IO uint32_t RESERVE1:16;
		} CR1;
	}; 
	
	union {							
		__IO uint32_t u32SSIEN;
		struct {
			__IO uint32_t EN : 1;
			__IO uint32_t RESERVE0:31; 
		} SSIEN;
	};
	
	union {							
		__IO uint32_t u32MWCTRL;
		struct {
			__IO uint32_t MOD : 1;			//0 非顺序传输		1 顺序传输
			__IO uint32_t DIR : 1;			//0 接收			1 发送
			__IO uint32_t MHS : 1;			//0 禁止握手		1 使能握手
			__IO uint32_t RESERVE0:29;
		}MWCTRL;
	};
	
	union {							
		__IO uint32_t u32SLAV;
		struct {
			__IO uint32_t SEL : 1;
			__IO uint32_t RESERVE0:31; 	
		} SLAV;
	};
	
	union {							
		__IO uint32_t u32BAUD;
		struct {
			__IO uint32_t DIV : 16;		//F_SSI = F_HCLK/DIV
			__IO uint32_t RESERVE0:16;
		} BAUD;
	};
	
	union {
		__IO uint32_t u32TXFIFO_LVL;
		struct {
			__IO uint32_t lvl : 3;
			__IO uint32_t RESERVE0:29;
		} TXFIFO_LVL;
	};
	
	union {	
		__IO uint32_t u32RXFIFO_LVL;
		struct {
			__IO uint32_t lvl : 3;
			__IO uint32_t RESERVE0:29;
		} RXFIFO_LVL;
	};
	
	union {	
		__I  uint32_t u32TXFIFO_CNT;
		struct {
			__I  uint32_t cnt : 3;
			__I  uint32_t RESERVE0:29;
		} TXFIFO_CNT;
	};

	union {				
		__I  uint32_t u32RXFIFO_CNT;
		struct {
			__I  uint32_t cnt : 3;
			__I  uint32_t RESERVE0:29;
		} RXFIFO_CNT;
	};

	union {							
		__I  uint32_t u32STAT;
		struct {
			__I  uint32_t BUSY : 1;
			__I  uint32_t TFNF : 1;		//TX FIFO Not Full
			__I  uint32_t TFE  : 1;		//TX FIFO Empty
			__I  uint32_t RFNE : 1;		//RX FIFO Not Empty
			__I  uint32_t RFF  : 1;		//RX FIFO Full
			__I  uint32_t TXE  : 1;		//TX Error
			__I  uint32_t DCOL : 1;		//Data Collision
			__I  uint32_t RESERVE0:25;
		} STAT;
	};
	
	union {							
		__IO uint32_t u32IEN;
		struct {
			__IO uint32_t TXEEN : 1;	//TX FIFO Empty
			__IO uint32_t TXOEN : 1;	//TX FIFO Overrun
			__IO uint32_t RXUEN : 1;	//RX FIFO Underrun
			__IO uint32_t RXOEN : 1;	//RX FIFO Overrun
			__IO uint32_t RXFEN : 1;	//RX FIFO Full
			__IO uint32_t MSTEN : 1;	//多主竞争
			__IO uint32_t RESERVE0:25;
		} IEN;
	};
	
	union {							
		__I  uint32_t u32ISR;
		struct {
			__I  uint32_t TXEIS : 1;	//TX FIFO Empty
			__I  uint32_t TXOIS : 1;	//TX FIFO Overrun
			__I  uint32_t RXUIS : 1;	//RX FIFO Underrun
			__I  uint32_t RXOIS : 1;	//RX FIFO Overrun
			__I  uint32_t RXFIS : 1;	//RX FIFO Full
			__I  uint32_t MSTIS : 1;	//多主竞争
			__I  uint32_t RESERVE0:25;
		}ISR;
	};
	
	union {							
		__I  uint32_t u32RIS;
		struct {
			__I  uint32_t TXEIS : 1;	//TX FIFO Empty
			__I  uint32_t TXOIS : 1;	//TX FIFO Overrun
			__I  uint32_t RXUIS : 1;	//RX FIFO Underrun
			__I  uint32_t RXOIS : 1;	//RX FIFO Overrun
			__I  uint32_t RXFIS : 1;	//RX FIFO Full
			__I  uint32_t MSTIS : 1;	//多主竞争
			__I  uint32_t RESERVE0:25;
		} RIS;
	};
	
	__I  uint32_t TXOICLR;				//读这个寄存器清除TXFIFO上溢中断
	__I  uint32_t RXOICLR;				//读这个寄存器清除RXFIFO上溢中断						
	__I  uint32_t RXUICLR;				//读这个寄存器清除RXFIFO下溢中断						
	__I  uint32_t MSTICLR;				//读这个寄存器清除多主竞争中断
	__I  uint32_t INTCLR;				//读这个寄存器清除以上四个中断
	
	__I  uint32_t RESERVE0[5];
												
	__IO uint32_t DATA;					
} SSI_T;

typedef struct 
{
	__IO uint32_t LOAD;
	__I  uint32_t CVAL;
	union {
		__IO uint32_t u32CTRL;
		struct {
			__IO uint32_t EN : 1;
			__IO uint32_t MODE : 1;
			__IO uint32_t IDIS : 1;		//1 禁止中断		0 使能中断
			__IO uint32_t RESERVE : 29;
		} CTRL;
	};

	__I  uint32_t ICLR;					//读取清中断标志
	__I	 uint32_t STAT;
} TIMR_T;

typedef struct {
	union {
		__IO uint32_t u32DAT0;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT0;
	};

	union {
		__IO uint32_t u32DAT1;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT1;
	};

	union {
		__IO uint32_t u32DAT2;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT2;
	};

	union {
		__IO uint32_t u32DAT3;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT3;
	};

	union {
		__IO uint32_t u32DAT4;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT4;
	};

	union {
		__IO uint32_t u32DAT5;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT5;
	};

	union {
		__IO uint32_t u32DAT6;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT6;
	};

	union {
		__IO uint32_t u32DAT7;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE0:4;
			__IO uint32_t VALID : 1;
			__IO uint32_t OVERRUN :1;
			__IO uint32_t RESERVE1:14;
		}DAT7;
	};

	__IO uint32_t DATB;					//Burst模式下相应通道最近的8个AD转化结果
	
	union {	
		__IO uint32_t u32CHER;
		struct {
			__IO uint32_t CH0_EN : 1;
			__IO uint32_t CH1_EN : 1;
			__IO uint32_t CH2_EN : 1;
			__IO uint32_t CH3_EN : 1;
			__IO uint32_t CH4_EN : 1;
			__IO uint32_t CH5_EN : 1;
			__IO uint32_t CH6_EN : 1;
			__IO uint32_t CH7_EN : 1;
			__IO uint32_t RESERVE:24;
		} CHER;
	};
	
	union {	
		__IO uint32_t u32CTRL;
		struct {
			__IO uint32_t ADC_ST : 1;
			__IO uint32_t ADC_EN : 1;
			__IO uint32_t RESERVE:30;
		} CTRL;
	};

	union { 
		__IO uint32_t u32MODE;
		struct {
			__IO uint32_t MOD_SS : 1;		//单次扫描模式
			__IO uint32_t MOD_CS : 1;		//连续扫描模式
			__IO uint32_t MOD_B  : 1;		//突发模式
			__IO uint32_t MOD_S  : 1;		//在指定通道上进行一次转换
			__IO uint32_t RESERVE:28;
		} MODE;
	};

	union {
		__IO uint32_t u32CMPR;
		struct {
			__IO uint32_t CMP_EN : 1;
			__IO uint32_t RESERVE0 : 1;
			__IO uint32_t CMP_COND : 1;		//比较条件	1 当结果>=CMPD时，匹配计数器增一	0 当结果<CMPD时，匹配计数器增一
			__IO uint32_t CMP_CHNL : 3;
			__IO uint32_t RESERVE1 : 2;
			__IO uint32_t MATCH_CNT: 4;		//匹配MATCH_CNT次后产生比较匹配中断
			__IO uint32_t RESERVE2 : 4;
			__IO uint32_t CMP_VALUE: 12;		
			__IO uint32_t RESERVE3 : 4;
		} CMPR;
	};

	union {
		__IO uint32_t u32IMSK;
		struct {
	   		__IO uint32_t EOC_ENA : 1;
			__IO uint32_t CMP_ENA : 1;
			__IO uint32_t RESERVE : 30;
		} IMSK;
	};

	union {
		__IO uint32_t u32STAT;
		struct {
			__IO uint32_t EOC : 1;
			__IO uint32_t CMP : 1;
			__IO uint32_t RESERVE0: 6;
			__IO uint32_t VALID : 8;
			__IO uint32_t OVERRUN : 8;
			__IO uint32_t RESERVE1: 8;
		} STAT;
	};
	
	union {
		__IO uint32_t u32ADC_TRIG;			//ADC触发源使能
		struct {
			__IO uint32_t PWM0A_TEN : 1;	//当PWM0通道A输出高电平开始延时，延时PWM0A_DLY个周期后触发ADC开始采集并转换模拟信号
			__IO uint32_t PWM1A_TEN : 1;	//当PWM1通道A输出高电平开始延时，延时PWM1A_DLY个周期后触发ADC开始采集并转换模拟信号
			__IO uint32_t PWM2A_TEN : 1;	//当PWM2通道A输出高电平开始延时，延时PWM2A_DLY个周期后触发ADC开始采集并转换模拟信号
			__IO uint32_t RESERVE1 : 29;
		} ADC_TRIG;
	};
	
	union {
		__IO uint32_t u32PWM0A_DLY;
		struct {
			__IO uint32_t CNT : 16;
			__IO uint32_t RESERVE1 : 16;	
		} PWM0A_DLY;
	};
	
	union {
		__IO uint32_t u32PWM1A_DLY;
		struct {
			__IO uint32_t CNT : 16;
			__IO uint32_t RESERVE1 : 16;
		} PWM1A_DLY;
	};
	
	union {
		__IO uint32_t u32PWM2A_DLY;
		struct {
			__IO uint32_t CNT : 16;
			__IO uint32_t RESERVE1 : 16;
		} PWM2A_DLY;
	};		
} ADC_T;

typedef struct 
{
	union {
		__IO uint32_t u32MODE;
		struct {
			__IO uint32_t COMPL : 1;	//0 普通输出			1 互补输出
			__IO uint32_t ALIGN : 1;	//0 左对齐输出模式		1 中心对齐输出魔兽
			__IO uint32_t RESERVE:30;	
		} MODE;
	};

	__IO uint32_t CycleA;				//A路周期，此为16位寄存器
	__IO uint32_t HDutyA;				//A路占空比，此为16位寄存器
	__IO uint32_t DeadZoneA;			//A路死区时长，此为16位寄存器
	__IO uint32_t CycleB; 
	__IO uint32_t HDutyB;
	__IO uint32_t DeadZoneB;
	__IO uint32_t RESERVE;	
} PWM_T;

typedef struct 
{
	union {
		__IO uint32_t u32CHEN;	
		struct {
			__IO uint32_t PWM0A_EN : 1;
			__IO uint32_t PWM0B_EN : 1;
			__IO uint32_t PWM1A_EN : 1;
			__IO uint32_t PWM1B_EN : 1;
			__IO uint32_t PWM2A_EN : 1;
			__IO uint32_t PWM2B_EN : 1;
			__IO uint32_t RESERVE0 :26;
		} CHEN;	
	};
	
	union {		
		__IO uint32_t u32IDIS;
		struct {
			__IO uint32_t PWM0A_H : 1;			//高电平结束
			__IO uint32_t PWM0B_H : 1;
			__IO uint32_t PWM1A_H : 1;
			__IO uint32_t PWM1B_H : 1;
			__IO uint32_t PWM2A_H : 1;
			__IO uint32_t PWM2B_H : 1;
			__IO uint32_t RESERVE0: 2;
			__IO uint32_t PWM0A_C : 1;			//新周期开始
			__IO uint32_t PWM0B_C : 1;
			__IO uint32_t PWM1A_C : 1;
			__IO uint32_t PWM1B_C : 1;
			__IO uint32_t PWM2A_C : 1;
			__IO uint32_t PWM2B_C : 1;
			__IO uint32_t RESERVE1:18;
		} IDIS;
	};

	union {
		__I  uint32_t u32STAT;
		struct {
			__I  uint32_t PWM0A_H : 1;			//高电平结束
			__I  uint32_t PWM0B_H : 1;
			__I  uint32_t PWM1A_H : 1;
			__I  uint32_t PWM1B_H : 1;
			__I  uint32_t PWM2A_H : 1;
			__I  uint32_t PWM2B_H : 1;
			__I  uint32_t RESERVE0: 2;
			__I  uint32_t PWM0A_C : 1;			//新周期开始
			__I  uint32_t PWM0B_C : 1;
			__I  uint32_t PWM1A_C : 1;
			__I  uint32_t PWM1B_C : 1;
			__I  uint32_t PWM2A_C : 1;
			__I  uint32_t PWM2B_C : 1;
			__I  uint32_t RESERVE1:18;
		} STAT;
	};

	__O  uint32_t ICLR;

} PWM_G_T;

typedef struct{
	union {
   		__IO uint32_t u32CTRL;
		struct {
			__IO uint32_t MASTER_EN : 1;
			__IO uint32_t SPEED_SEL : 2;		//1 标准速度		2 快速速度		3 高速速度
			__IO uint32_t ADDR_SLAV : 1;		//当为丛机时，选择地址模式	0 7位地址		1 10位地址 
			__IO uint32_t ADDR_MSTR : 1;		//当为主机时，选择地址模式	0 7位地址		1 10位地址
			__IO uint32_t RESTART_EN: 1;
			__IO uint32_t SLAVE_DIS : 1;		//从机禁能
			__IO uint32_t RESERVE  : 25; 
		} CTRL;
	};

	union {
		__IO uint32_t u32TADDR;
		struct {
			__IO uint32_t ADDR : 10;			//当为主机时，设置目标地址
			__IO uint32_t GC_OR_STA : 1;		//若位[11]置位为1，则执行这一位		0 广播地址		1 开始字节
			__IO uint32_t SPECIAL	: 1;		//0 忽略位[10]，正常使用寄存器TAR		1 执行特殊的I2C命令在GC_OR_STA位置位
			__IO uint32_t RESERVE	:20;	
		} TADDR;
	};

	union {
		__IO uint32_t u32SADDR;
		struct {
			__IO uint32_t ADDR : 10;			//当为从机时，设置从机地址
			__IO uint32_t RESERVE : 22;
		} SADDR;
	};

	__IO uint32_t HS_MADDR;
   	
	__IO uint32_t DATA_CMD;		//[8]	只写，
							   	//注意：在IIC使能之前写此寄存器将导致写如的数据丢失
	__IO uint32_t SS_SCL_HCNT;
	__IO uint32_t SS_SCL_LCNT;
	__IO uint32_t FS_SCL_HCNT;
	__IO uint32_t FS_SCL_LCNT;
	__IO uint32_t HS_SCL_HCNT;
	__IO uint32_t HS_SCL_LCNT;


	union {
		__I	 uint32_t u32ISR;
		struct {
	   		__I	 uint32_t RX_UNDER : 1;
			__I	 uint32_t RX_OVER  : 1;
			__I	 uint32_t RX_FULL  : 1;
			__I	 uint32_t TX_OVER  : 1;
			__I	 uint32_t TX_EMPTY : 1;
			__I	 uint32_t RD_REQ   : 1;
			__I	 uint32_t TX_ABRT  : 1;
			__I	 uint32_t RX_DONE  : 1;
			__I	 uint32_t ACTIVITY : 1;
			__I	 uint32_t STOP_DET : 1;
			__I	 uint32_t STAR_DET : 1;
			__I	 uint32_t GEN_CALL : 1;
			__I	 uint32_t RESERVE  :20;
		} ISR;
	};

	union {
		__IO uint32_t u32IMSK;				//=0   屏蔽中断，中断禁能
		struct {							//=1 不屏蔽中断，中断使能 
			__IO uint32_t RX_UNDER : 1;
			__IO uint32_t RX_OVER  : 1;
			__IO uint32_t RX_FULL  : 1;
			__IO uint32_t TX_OVER  : 1;
			__IO uint32_t TX_EMPTY : 1;
			__IO uint32_t RD_REQ   : 1;
			__IO uint32_t TX_ABRT  : 1;
			__IO uint32_t RX_DONE  : 1;
			__IO uint32_t ACTIVITY : 1;
			__IO uint32_t STOP_DET : 1;
			__IO uint32_t STAR_DET : 1;
			__IO uint32_t GEN_CALL : 1;
			__IO uint32_t RESERVE  :20;
		}IMSK;
	};

	union {
		__I  uint32_t u32RIS;
		struct {
			__I	 uint32_t RX_UNDER : 1;			
			__I	 uint32_t RX_OVER  : 1;			
			__I	 uint32_t RX_FULL  : 1;
			__I	 uint32_t TX_OVER  : 1;
			__I	 uint32_t TX_EMPTY : 1;
			__I	 uint32_t RD_REQ   : 1;			//作为从机时：主机试图从I2C读取数据，此位变为1，I2C总线保持在等待状态（SCL=0）直到这个中断发生
			__I	 uint32_t TX_ABRT  : 1;			//作为发送者：读TX_ABRT_SOURCE获取产生ABART的原因
			__I	 uint32_t RX_DONE  : 1;			//作为从机时：主机不确认发送的字节，此位置1
			__I	 uint32_t ACTIVITY : 1;
			__I	 uint32_t STOP_DET : 1;			//指示总线上出现了一个停止信号(主从、收发皆可用)
			__I	 uint32_t STAR_DET : 1;			//指示总线上出现了一个开始或重新开始信号(主从、收发皆可用)
			__I	 uint32_t GEN_CALL : 1;			//接收到并且接受了一个广播地址
			__I	 uint32_t RESERVE  :20;
		} RIS;
	};
	
	union {
		__IO uint32_t u32RXFIFO_LVL;
		struct {
			__IO uint32_t LVL : 3;
			__IO uint32_t RESERV : 29;
		} RXFIFO_LVL;
	};
	
	union {
		__IO uint32_t u32TXFIFO_LVL;
		struct {
			__IO uint32_t LVL : 3;
			__IO uint32_t RESERV : 29;
		} TXFIFO_LVL;
	};

	__I	 uint32_t CLR_INTR;						//读将清除所有中断和TX_ABRT_SOURCE
	__I	 uint32_t CLR_RX_UNDER;
	__I	 uint32_t CLR_RX_OVER;
	__I	 uint32_t CLR_TX_OVER;
	__I	 uint32_t CLR_RD_REQ;
	__I	 uint32_t CLR_TX_ABRT;
	__I	 uint32_t CLR_RX_DONE;
	__I	 uint32_t CLR_ACTIVITY;
	__I	 uint32_t CLR_STOP_DET;
	__I	 uint32_t CLR_START_DET;
	__I	 uint32_t CLR_GEN_CALL;
	
	union {
		__IO uint32_t u32ENABLE;			//写1使能I2C模块
		struct {
			__IO uint32_t ENA : 1;
			__IO uint32_t RESERVE : 1;
		}ENABLE;
	};

	union {
		__I	 uint32_t u32STATUS;
		struct {
			__I	 uint32_t ACTIVITY : 1;
			__I	 uint32_t TFNF : 1;
			__I	 uint32_t TFE  : 1;
			__I	 uint32_t RFNE : 1;
			__I	 uint32_t RFF  : 1;
			__I	 uint32_t MSTR_ACTIVITY : 1;
			__I	 uint32_t SLAV_ACTIVITY : 1;
			__I	 uint32_t RESERVE : 25;
		} STATUS;
	};

	__I	 uint32_t TXFIFO_CNT;
	__I	 uint32_t RXFIFO_CNT;

	__IO uint32_t SDA_HOLD;

	union {
		__I	 uint32_t u32TX_ABRT_SOURCE;
		struct {
			__I	 uint32_t ABRT_7B_ADDR_NOACK : 1;
			__I	 uint32_t ABRT_10ADDR1_NOACK : 1;
			__I	 uint32_t ABRT_10ADDR2_NOACK : 1;
			__I	 uint32_t ABRT_TXDATA_NOACK  : 1;
			__I	 uint32_t ABRT_GCALL_NOACK   : 1;
			__I	 uint32_t ABRT_GCALL_READ    : 1;
			__I	 uint32_t ABRT_HS_ACKDET     : 1;	//High Speed Master code was acknowledged(wrong behavior) 
			__I	 uint32_t ABRT_SBYTE_ACKDET  : 1;	//The Start Byte was acknowledged(wrong behavior)
			__I	 uint32_t ABRT_HS_NORSTRT    : 1;	//restart is disabled but trying to use in High Speed Mode
			__I	 uint32_t ABRT_SBYTE_NORSTRT : 1; 	//restart is disabled but trying to send a START Byte
			__I	 uint32_t ABRT_10B_RD_NORSTRT: 1;	//restart is disabled but trying to sends a read command in 10-bit addressing mode
			__I	 uint32_t ABRT_MASTER_DIS    : 1; 	//trying to initiate a Master operation with the Master mode disabled
			__I	 uint32_t ARB_LOST : 1;				//Master has lost arbbitration
			__I	 uint32_t ABRT_SLVFLUSH_TXFIFO:1;
			__I	 uint32_t ABRT_SLV_ARBLOST  : 1;
			__I	 uint32_t ABRT_SLVRD_INTX   : 1;
			__I	 uint32_t RESERVE : 16;
		} TX_ABRT_SOURCE;
	};

	union {
		__IO uint32_t u32SLV_NACK;
		struct {
			__IO uint32_t NACK : 1;			//工作于从机状态时，产生一个NACK信号
			__IO uint32_t RESERVE : 31;	
		} SLV_NACK;
	};

	__I  uint32_t RESERVE[3];

	__IO uint32_t SDA_SETUP;

	union {
		__IO uint32_t u32ACK_GEN_CALL;
		struct {
			__IO uint32_t ACK : 1;			//置位时，当接收到一个广播时，将应答一个ACK；
			__IO uint32_t RESERVE : 31;		//清零时，I2C从机不产生广播中断
		} ACK_GEN_CALL;
	};

	__I  uint32_t ENABLE_STATUS;
} I2C_T;


typedef struct{
	union {
		__IO uint32_t u32CR;
		struct {
			__IO uint32_t EN : 1;
			__IO uint32_t RMOD : 1;		//0 超时即复位		1 第一次超时产生中断，若产生第二次超时时，没有清除中断，则系统复位
			__IO uint32_t RESERVE : 30;
		} CR;
	};
	
	union { 						
		__IO uint32_t u32TORR;
		struct {
			__IO uint32_t TOP : 4;
			__IO uint32_t TOP_INIT : 4;
			__IO uint32_t RESERVE  :24;
		} TORR; 
	};
	            		
	__I  uint32_t CCVR;             		
	__O  uint32_t CRR;					//写0x76重启计数器						
	__I  uint32_t STAT;             		
	__I  uint32_t ICLR;							
} WDT_T;


typedef struct {
	union {
		__IO uint32_t u32CLK_CFG;
		struct{
			__IO uint32_t CoreCLK_DIV : 8;		//=0：2分频			=奇数：不分频		=偶数 分频
			__IO uint32_t ADC_CLK_DIV : 4;		//=0：2分频			=奇数：不分频		=偶数 分频，直接对时钟源分频，不依赖于内核时钟
			__IO uint32_t PWM_CLK_DIV : 8;		//=0：2分频			=奇数：不分频		=偶数 分频，直接对时钟源分频，不依赖于内核时钟
			__IO uint32_t BOD_INT : 3;			//掉电中断级别：000 1.9V		001 2.3V		011 2.6V		111 2.9V		
			__IO uint32_t BOD_RST : 3;			//掉电复位级别：000 1.7V		001 2.1V		011 2.4V		111 2.7V
			__IO uint32_t TMR_COUNTR0 : 1;		//1:timer 0:counter
			__IO uint32_t TMR_COUNTR1 : 1;		//1:timer 0:counter
			__IO uint32_t TMR_COUNTR2 : 1;		//1:timer 0:counter
			__IO uint32_t TMR_COUNTR3 : 1;		//1:timer 0:counter
			__IO uint32_t TRIM_STARTE : 1;
			__IO uint32_t CLK_SRC     : 1;		//1: 内部RC 0: 外部晶振
		} CLK_CFG;
	};

	union {
		__IO uint32_t u32PCLK_EN;
		struct{
			__IO uint32_t TMR_CLK : 1;
			__IO uint32_t UART_CLK: 1;
			__IO uint32_t RESERVE1: 1;
			__IO uint32_t SSI_CLK : 1;
			__IO uint32_t WDT_CLK : 1;
			__IO uint32_t ADC_CLK : 1;
            __IO uint32_t RESERVE2: 1;
			__IO uint32_t PWM_CLK : 1;
			__IO uint32_t PID_CLK : 1;
			__IO uint32_t RESERVE3:23;
		} PCLK_EN;
	};
    
    union{
        __IO uint32_t u32DBL_IRC;
        struct{
            __IO uint32_t DBL_IRC : 1;      //0 22MHz       1 44MHz
            __IO uint32_t RESERVE :31;
        } DBL_IRC;
    };

    union{
        __IO uint32_t u32SPI_CONNECT;
        struct{
            __IO uint32_t CONNECT : 1;      //0 connect     1 not connect
            __IO uint32_t RESERVE :31;
        } SPI_CONNECT;
    };

    __I  uint32_t CHIPID_0;									
    __I  uint32_t CHIPID_1;	
    __I  uint32_t CHIPID_2;	
    __IO uint32_t RESERVE1;

    union{
        __IO uint32_t u32OSC_TRIM_LO;					
        struct{												
            __IO uint32_t TRIM_VALUE  :25;
            __IO uint32_t TRIM_GATING : 1;
            __IO uint32_t TRIM_CLKSRC : 1;
            __IO uint32_t RESERVE     : 5;
        } OSC_TRIM_LO;
    };

    union{
        __IO uint32_t u32OSC_TRIM_HI;
        struct{
            __IO uint32_t TRIM_VALUE  :25;
            __IO uint32_t TRIM_GATING : 1;
            __IO uint32_t TRIM_CLKSRC : 1;
            __IO uint32_t RESERVE     : 5;
        } OSC_TRIM_HI;
    };

    __IO uint32_t SPI_FLASH_EX;									
    __IO uint32_t SPI_FLASH_ID;

    union{
        __IO uint32_t u32MEM_CONF;
        struct{	
            __IO uint32_t MEM_CONF : 2;     //00=16/2   01=14/4     10=12/6	    11=17.5/0.5
            __IO uint32_t RESERVE  :29;
        } MEM_CONF;
    };

    __IO uint32_t RESERVE2;
    __IO uint32_t RESERVE3;
    __IO uint32_t RESERVE4;	
} SYS_T;

typedef struct {
	union {
		__IO uint32_t u32PID_EN;
		struct {
			__IO uint32_t EN : 1;
			__IO uint32_t RESERVE : 31;
		} PID_EN;		
	};
	
	union {
		__IO uint32_t u32INT_MASK;
		struct {
			__IO uint32_t INT_DIS : 1;
			__IO uint32_t RESERVE : 31;
		} INT_MASK;
	};
	
	union {
		__I  uint32_t u32INT_FLAG;
		struct {
			__I  uint32_t INT : 1;
			__I  uint32_t RESERVE : 31;
		} INT_FLAG;
	};
	
	union {
		__IO uint32_t u32ADC_MASK;
		struct {
			__IO uint32_t ADC_DIS : 1;
			__IO uint32_t RESERVE : 31;
		} ADC_MASK;
	};
	
	union {
		__IO uint32_t u32START_PID;
		struct {
			__IO uint32_t LIMIT : 13;
			__IO uint32_t RESERVE : 19;
		} START_PID;
	};
	
	union {
		__IO uint32_t u32ADC_AVG_ARG;
		struct {
			__IO uint32_t ARG : 2;
			__IO uint32_t RESERVE : 30;
		} ADC_AVG_ARG;
	};
	
	__I  uint32_t RESERVE0[5];

	union {
		__IO uint32_t u32PID_K0;
		struct {
			__IO uint32_t VALUE : 13;
			__IO uint32_t RESERVE : 19;
		} PID_K0;
	};
	
	union {
		__IO uint32_t u32PID_K1;
		struct {
			__IO uint32_t VALUE : 13;
			__IO uint32_t RESERVE : 19;
		} PID_K1;
	};
	
	union {
		__IO uint32_t u32PID_K2;
		struct {
			__IO uint32_t VALUE : 13;
			__IO uint32_t RESERVE : 19;
		} PID_K2;
	};
	
	union {
		__IO uint32_t u32PID_SETPOINT;
		struct {
			__IO uint32_t VALUE : 13;
			__IO uint32_t RESERVE : 19;
		} PID_SETPOINT;
	};
	
	union {
		__IO uint32_t u32PWM_WIDTH;
		struct {
			__IO uint32_t SEL : 2;
			__IO uint32_t RESERVE : 30;
		} PWM_WIDTH;
	};
	
	union { 
		__IO uint32_t u32PID_CLK_DIV;
		struct {
			__IO uint32_t COUNT : 16;
			__IO uint32_t RESERVE : 16;
		} PID_CLK_DIV;
	};
	
	union { 
		__IO uint32_t u32IN_DATA;
		struct {
			__IO uint32_t VALUE : 13;
			__IO uint32_t RESERVE : 19;
		} IN_DATA;
	};
	
	union {
		__IO uint32_t u32U_SHIFT;
		struct {
			__IO uint32_t VALUE : 2;
			__IO uint32_t RESERVE : 30;
		} U_SHIFT;
	};
	
	__I  uint32_t RESERVE1[2];
	
	union {
		__I  uint32_t u32PID_ERR0;
		struct {
			__I  uint32_t VALUE : 12;
			__I  uint32_t RESERVE : 20;
		} PID_ERR0;
	};
	
	union {
		__I  uint32_t u32PID_ERR1;
		struct {
			__I  uint32_t VALUE : 12;
			__I  uint32_t RESERVE : 20;
		} PID_ERR1;
	};

	union {
		__I  uint32_t u32PID_ERR2;
		struct {
			__I  uint32_t VALUE : 12;
			__I  uint32_t RESERVE : 20;
		} PID_ERR2;
	};

	union {
		__I  uint32_t u32PID_U1;
		struct {
			__I  uint32_t VALUE : 25;
			__I  uint32_t RESERVE : 7;
		} PID_U1;
	};
	
	union {
		__I  uint32_t u32PID_U;
		struct {
			__I  uint32_t VALUE : 25;
			__I  uint32_t RESERVE : 7;
		} PID_U;
	};
	
	__I  uint32_t RESERVE2[15];
	
	union {
		__IO uint32_t u32PID_CLK_DIV_EN;
		struct {
			__IO uint32_t EN : 1;
			__IO uint32_t RESERVE : 31;
		} PID_CLK_DIV_EN;
	};
	
	union {
		__IO uint32_t u32MAX_ERR;
		struct {
			__IO uint32_t VALUE : 12;
			__IO uint32_t RESERVE : 30;
		} MAX_ERR;
	};
	
} PID_T;

/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/
#define SRAM_BASE				((	uint32_t) 0x20000000)
#define PERIPH_BASE				((  uint32_t) 0x40000000)
#define SYSCTL_BASE				((	uint32_t) 0x400F0000)

#define PORT_BASE               (PERIPH_BASE	+ 0x0000)
#define GPIO_BASE				(PERIPH_BASE	+ 0x1000)
#define EXTI_BASE				(PERIPH_BASE	+ 0x1030)
#define TIMR_BASE				(PERIPH_BASE   	+0x12000)
#define UART_BASE				(PERIPH_BASE   	+ 0x3000)
#define SSI_BASE				(PERIPH_BASE   	+ 0x4000)
#define ADC_BASE				(PERIPH_BASE	+0x17000)
#define PWM_BASE				(PERIPH_BASE   	+0x16000)
#define WDT_BASE				(PERIPH_BASE   	+0x19000)
#define PID_BASE				(PERIPH_BASE   	+0x20000)

#define GPIOA_BASE				(GPIO_BASE		+ 0x0000)
#define GPIOB_BASE				(GPIO_BASE		+ 0x000C)
#define GPIOC_BASE				(GPIO_BASE		+ 0x0018)
#define GPIO_EXTA_BASE			(GPIO_BASE		+ 0x0050)
#define GPIO_EXTB_BASE			(GPIO_BASE		+ 0x0054)
#define GPIO_EXTC_BASE			(GPIO_BASE		+ 0x0058)

#define EXTIA_BASE				(EXTI_BASE		+ 0x0000)

#define TIMR0_BASE				(TIMR_BASE		+ 0x0000)	
#define TIMR1_BASE				(TIMR_BASE		+ 0x0014)
#define TIMR2_BASE				(TIMR_BASE		+ 0x0028)
#define TIMR3_BASE				(TIMR_BASE		+ 0x003C)

#define PWM0_BASE				(PWM_BASE 		+ 0x0000) 
#define PWM1_BASE				(PWM_BASE 		+ 0x0020) 
#define PWM2_BASE				(PWM_BASE 		+ 0x0040) 
#define PWMG_BASE				(PWM_BASE 		+ 0x0080) 


/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/
#define SYS							((SYS_T *)SYSCTL_BASE)

#define PORT                        ((PORT_T *) PORT_BASE)

#define UART				  		((UART_T *) UART_BASE)

#define SSI							((SSI_T  *) SSI_BASE )
#define ADC							((ADC_T  *) ADC_BASE )
#define WDT							((WDT_T  *) WDT_BASE )

#define PID							((PID_T  *) PID_BASE )

#define GPIOA				  	  	((GPIO_T *) GPIOA_BASE)
#define GPIOB				  	  	((GPIO_T *) GPIOB_BASE)
#define GPIOC				  	  	((GPIO_T *) GPIOC_BASE)
#define GPIO_EXTA					((GPIO_EXT_T *) GPIO_EXTA_BASE)
#define GPIO_EXTB					((GPIO_EXT_T *) GPIO_EXTB_BASE)
#define GPIO_EXTC					((GPIO_EXT_T *) GPIO_EXTC_BASE)


#define EXTIA						((EXTI_T *) EXTIA_BASE)

#define TIMR0 				  		((TIMR_T *) TIMR0_BASE)	
#define TIMR1						((TIMR_T *) TIMR1_BASE)	
#define TIMR2						((TIMR_T *) TIMR2_BASE) 			
#define TIMR3						((TIMR_T *) TIMR3_BASE)
	
#define PWM0 				  		((PWM_T  *) PWM0_BASE)	
#define PWM1 				  		((PWM_T  *) PWM1_BASE)
#define PWM2 				  		((PWM_T  *) PWM2_BASE)
#define PWMG				  		((PWM_G_T*) PWMG_BASE)


#include "SWM120_gpio.h"
#include "SWM120_exti.h"
#include "SWM120_timr.h"
#include "SWM120_uart.h"
#include "SWM120_adc.h"
#include "SWM120_cmp.h"
#include "SWM120_opa.h"
#include "SWM120_ssi.h"
#include "SWM120_pwm.h"
#include "SWM120_wdt.h"
#include "SWM120_flash.h"


#endif //__SWM120_H__
